Supporting U-Type

1Learning Outcomes¶

• Implement a datapath that supports U-Type instructions (lui and auipc).

• Explain why the ALU (in our course datapath) needs to support wiring the input B directly to its output.

At this point, we have a datapath that can support R-, I-, S-, B-, and J-Type instructions. There is just one instruction format left: the U-Type (upper immediate) instruction. Review U-Type instructions before continuing.

2Updates needed for U-Type¶

To support U-Type:

• RegFile: We read no registers but write one register rd.

• PC: We read from and write to PC. The value to write is pc + 4.

There are two updates we need to make:

• The immediate generator must now support immediates in U-Type instructions.

• The ALU must support passing the immediate through (i.e., select only ALU input B and ignore input A). This operation is needed for the lui instruction.

3Tracing the lui Datapath¶

1. Instruction Fetch: At the beginning of the clock cycle, read PC and fetch the current instruction from IMEM.

   Before the next rising clock edge, set pc + 4 to the input of PC.

2. Instruction Decode: Build the immediate imm for U-Type instructions. Also configure control logic (see below).

3. Execute: Get the value imm and set as the ALU output.

4. Memory: (We don’t access DMEM, so skip this.)

5. Write Back: Write the ALU output to the destination register and connect output of the WBSel mux to RegFile’s wdata input.

   Around the next rising clock edge, wdata, RegWEn, and rd should be held stable through setup and hold time of RegFile.

4Tracing the auipc Datapath¶

1. Instruction Fetch: At the beginning of the clock cycle, read PC and fetch the current instruction from IMEM. Feed pc to EX phase.

   Before the next rising clock edge, set pc + 4 to the input of PC.

2. Instruction Decode: Build the immediate imm for U-Type instructions. Also configure control logic (see below).

3. Execute: Compute pc + imm using the ALU. Because control signals are ASel=1 and BSel=1, the two muxes before the ALU will select pc and imm, respectively. Because ALUSel=Add, the ALU will add these two values together.

4. Memory: (We don’t access DMEM, so skip this.)

5. Write Back: Write the ALU output to the destination register and connect output of the WBSel mux to RegFile’s wdata input.

   Around the next rising clock edge, wdata, RegWEn, and rd should be held stable through setup and hold time of RegFile.