Supporting Immediates

1Learning Outcomes¶

• Implement a datapath that supports R-Type and I-Type arithmetic/logical instructions by reusing the ALU and adding an immediate generator block.

• Explain why a MUX is needed at the B input of the ALU.

• Design an immediate generator block that outputs a 32-bit immediate value from a 32-bit instruction.

• Extend the immediate generator block to support multiple immediate formats based on instruction format: I-, S-, B-, J-, and U-Type.

2Building a R-Type + addi processor¶

Let’s extend our R-Type datapath to support I-Type arithmetic and logical instructions, starting with addi. To support addi:

• RegFile: We read one register rs1 and write one register rd. The value to write is R[rs1] + imm, the sum of the read register value and an immediate.

• PC: We read from and write to PC. The value to write is pc + 4.

The addi instruction updates the same two states as R-Type instructions. But we now need to build an immediate imm!

To do so, we reuse what already exists in our R-Type datapath, then consider what additional blocks we need to add. In Figure 1, we notice:

• We can leave the PC = PC + 4 portion of the datapath unchanged.

• We can reuse much of the read/writing of the RegFile portion of the datapath. We still want to read R[rs1] and write R[rd].

• We want add two 32-bit values, so we should probably reuse the ALU to “add.”

  • We can keep the wire to ALU’s input signal A unchanged.

  • We want to change the input signal B to be set to an immediate imm so that the ALU computes alu = R[rs1] + imm.

We therefore need additional logic that, for I-Type instructions, feeds in an immediate imm to ALU input B (instead of R[rs2], used for R-Type). Figure 2 introduces the two new blocks and wires them to our existing datapath:

1. A new mux selects the ALU input B based on a new control signal BSel. Read about muxes/multiplexors in a previous section.

   • Set BSel to 1 to pass in the immediate imm.

   • Set Bsel to 0 to pass in the register value R[rs2].

2. A new block, the immediate generator, generates a 32-bit value imm from the instruction bits inst.

3Tracing the addi Datapath¶

Let’s walk through the addi datapath with this new knowledge.

1. Instruction Fetch: Increment PC to next instruction (see R-Type datapath). Read the instruction inst from IMEM.

2. Instruction Decode:

   • Read R[rs1] from RegFile (see R-Type).

   • Set up the destination register rd for writing.

   • Build the immediate imm. For I-Type instructions, wire the upper 12 bits of the instruction inst[31:20] to the input to the Immediate Generator block.

   • Configure control logic.

     • Configure ImmSel to I-type immediates (for now, we only have one type of immediate).

     • Set RegWEn to 1.

     • Set BSel to 1.

     • Set ALUSel to Add.

   After some delay, the immediate generator block updates its output signal imm to the appropriate sign-extended 32-bit immediate value, register value R[rs1] is read, and control signals are set.

3. Execute: Because the control line BSel=1 selects the generated immediate imm for ALU input B, our ALU computes R[rs1] + imm.

4. Memory: (We don’t access DMEM, so skip this.)

5. Write Back: Write ALU output to the destination register by connecting alu to RegFile’s wdata input (see R-Type).

   Around the next rising clock edge, wdata, RegWEn, and rd should be held stable through setup and hold time of RegFile.

4Immediate Generator Block¶

We encourage revisiting this section after reading a few more example datapath traces.

Recall that the bits of the immediate are stored in different bits of the instruction, depending on the type of the instruction. The ImmSel signal, which is implemented in the control logic, will determine which type of immediate this subcircuit should generate.

The immediate storage formats are listed below in Table 2.

Observations/reminders:

• You should treat I*-type immediates as I-type immediates, since the ALU should only use the lowest 5 bits of the B input when computing shifts.

• Recall that all immediates are 32 bits and sign-extended. Sign extension is shown in Table 2 as inst[31] repeated in the upper bits.

• U-type instructions require left-shifting the immediate by 12 bits (e.g. lui is written as rd = imm << 12 on the reference card). This should be done in the immediate generator so that the datapath doesn’t need to perform any extra shifting.

In the following subsections, we “iteratively” build the immediate generator to support I-Type, then S-Type, then B-Type. We leave the implementation of J-Type and U-Type immediates to you and the course project.

4.1I-Type¶

First, suppose our datapath only supported immediates from I-Type instructions. In this case, the immediate generator would perform two operations as shown in Figure 5.

4.2I-Type, S-Type¶

Next, suppose our datapath supported immediates from both I-Type and S-Type instructions. The immediate generator must set the lower bits imm[4:0] based on the immediate type. In Figure 6, we implement this selection with a MUX.

4.3I-Type, S-Type, B-Type¶

Finally, suppose our datapath supports I-Type, S-Type, and B-Type instructions. The immediate generator design is shown in Figure 7, now with even more MUXes.

4.4Course Project Details¶